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spm1006 version 1.5 mar ch 16, 2016 page 1 of 22 4 - 2 8 v i n put 8 a o utput power supply in inductor (psi 2 ) module features ? integrated point of load power module using psi 2 power supply in inductor technology ? small footprint, low - p rofile, 15mm x 9mm x 3 mm, with lga package (0. 63 mm pads) ? efficiency of 94 % a t 4 a and 9 3 % at 6 a for 5v output , 12v input ? up to 8a maximum output current ; up to 6a at 85c ambient with no air flow ? 4 % output voltage regulation ? single resistor output voltage programming for voltages from 0. 6 v to 5v ? output voltage remote sensing ? input voltage range 4v to 28v ? pre - bias start up capability ? enable signal input and power good signal output ? output voltage sequencing ? programmable under voltage lock out (uvlo) ? output over - c urrent protection (ocp) ? operating temperature r ange - 40c to 85c ? qua lified to ipc9592b, class ii ? msl3 and rohs compliant applications ? broadband and communications e quipment ? dsp and fpga point of load a pplications ? high density distributed power s ystems ? aut omated pci / pci express / pxi e xpress ? automated test and medical e qu ipment description spm1006 is an easy - to - use 8 a output integrated point of load (pol) power supply module . it contains power mosfets, driver, pwm controller, a high performance inductor, input and output capacitors and other passive components in one low p rofile lga package using psi 2 technology . only one external input capac itor and one external output capacitor are needed for typical application s . there is no need for loop compensation, sensitive pcb layout, inductor selection, or in - circuit production t esting. the spm1006 can be programmed for any output voltage between 0.6v and 5.0v using a single external resistor . for an output voltage of 0.6v no resistor is required. the spm100 6 deliver s up to 8 a load current , and can deliver up to 6 a at 85c ambien t temperature with no airflow. small size ( 15mm x 9mm ) and low profile ( 3 mm ) allows the spm1006 to be placed very close to its load , or on the back side of the pcb board for high density application s . instant pwm control is used to achieve excellent trans ient response to line and load changes without sacrificing stability and high efficiency at light load. sumida's psi 2 technology ensures optimal inductor design , uniform temperature distribution and very low temperature difference between case and ic die. simplified application efficiency vs load current e n v a u x s e n s e p g n d p w r g d v a d j v o u t p v i n a g n d v o u t v i n c i n s p m 1 0 0 6 c o u t p h a s e r a d j 4 - 2 8 v
spm1006 version 1.5 mar ch 16, 2016 page 2 of 22 absolute maximum (1) ratings over operating temperature range (unless otherwise noted) value unit min max inputs p vin - 0.3 30 v en - 0.3 30 v v sense - 0.3 30 v vadj - 0.3 4 v output s vou t - 0.6 pvin v phase - 0.6 pvin v pwrgd - 0.3 30 v vaux - 0.3 4 v temperature operating junction temperature - 40 150 c storage temperature - 65 150 c lead temperature (10 seconds max) 260 c (1 ) stresses beyond these absolute maximum ratings may cause permanent damage to the d evice. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indica ted under recommended operating conditions is not implied. exposure to absolute - maximum - rated co nditions for extended periods may affect device reliability.
spm1006 version 1.5 mar ch 16, 2016 page 3 of 22 electrical characteristics the electrical performance is based on the following conditions unless otherwise stated: 25 c ambient temperature, no air flow; v in = 12 v, i out = 6 a, c in = 4x 22 f c eramic, c out = 2x 1 0 0 f ceramic . parameters test conditions min typ max unit input specifications v in i nput voltage [ note 1 ] over i out range 4 12 28 v v start start up voltage [ note 2 ] over i out range 3. 6 5 v v en_on enable on voltage enable high volta ge (module turned on) 0.8 v v en_off enable off voltage enable low voltage (module turned off) 0.4 v i stby input standby current en pin to p gnd (shut down) 0.3 m a en = 2v, i out = 0a 1.5 m a uvlo under voltage lock out [ note 2 ] 3.55 v uvlo hy steresis 0. 1 v output specifications i out : o utput continuous current t a = - 40c to 85c, natural convection 0 6 a i out : maximum current t a = - 40c to 50 c , refer to fig. 28 - fig. 30 8 a v out set point accuracy [ note 3 ] t a = 25c, v in = 12v, i out = 3a 1 .5% temperature variation - 40c < t a < +85c, i out = 3a 1 % line regulation over v in range, t a = 25c, i out = 3a 0.5% load regulation over i out range, t a = 25c, v in = 12v 1% total variation [ note 3 ] set - point, line, load, temperature variation 4 % v out(adj) : output voltage adjust range over i out range [ note 4 ] 0.6 5 .5 v v o_rip , output voltage ripple 20mhz bandwidth, v in = 12v, i out = 6a 20 mvpp v aux : auxiliary output output voltage 3.3 v output current 10 ma ovp over - v oltage protection ovp threshold (percentage of nominal) 11 5 % 120% 12 5 % ovp shutdown delay 2 0 s pwrgd power good signal v out rising (% of v out ) pwrgd high 88 % 90 % 92 % pwrgd delay 10 s v out falling (% of v out ) hysteresis 2% f s switching frequency v in = 12v, v out = 5v, i out = 6 a 76 0 khz performance specifications efficiency ( v out = 5v ) v in = 12v i out = 3a 9 4 .2% i out = 6a 9 3. 2 % tran sient response (v out = 5v) 1a/s load step between 3 a and 6 a over/undershoot 5 5 mv recovery time 1 5 0 s soft - start time v in = 12v, over i out range 5 00 s current limit and thermal specifications i lim current limit point v in = 12v 8 11 a therm al shutdown (die temperature) thermal shutdown 150 c thermal shutdown recovery hysteresis 15 c note 1: input voltage must be at least 1.5v higher than the output voltage note 2 : startup voltage and uvlo are with no external resistor ; startup and u vlo can be increased using an external programming resistor C refer to startup voltage on page 13 . note 3 : with 0.1% tolerance external voltage set resistor . note 4 : for applications requiring output voltage higher than 5v , pl ease consult sumida.
spm1006 version 1.5 mar ch 16, 2016 page 4 of 22 power module information functional block diagram for spm1006 v a d j v s e n s e v o u t p g n d e n p w r g d p v i n p g n d a g n d v a u x p h a s e c i n c a u x c o u t p w m c o n t r o l l e r a n d f e t d r i v e 0 . 6 v 0 . 8 v r 1 r 2
spm1006 version 1.5 mar ch 16, 2016 page 5 of 22 pin descriptions pin name description p vin ( a3, b3, c3, d3, e3, f3, g2 - g3) input voltage pin s , referenced to pgnd . connect input ceramic capacitors between the se pins and pgnd p lane, close to the power module . it is suggest to place the ceramic capacitor s at both sides of the module, one between pin a3 and pin a4 - a5 and one between pin g2 - g3 and pin g4 - g5 . v aux (a 1, b 1) auxiliary output from an ldo in the modul e, which is referenced to agnd. an external capacitor is not normally necessary but can be added if required. note: vaux pin can only provide 1 0 ma maximum current. phase (a6 - a 8) switching no d e of the buck converter . please connect these pins together us ing a small and isolated copper plane under the device for better thermal performance . do not connect any external component to these pin s . d o not use these pins for other functions. vout (e6 - e 11, f 6 - f 11, g 6 - g 11) output voltage pins. connect these pins to gether onto a copper plane. connect external output filter capacitors between these pin s and pgnd plane, close to the device. pgnd (a4 - a5, a9 - a11, b4 - b11, c4 - c11, d4 - d11, e4, f4 - f5, g4 - g5) zero dc voltage reference for power circuitry . these pins should b e connected directly to the pcb ground plane. all pins must be connected together externally with a copper plane or pour ed directly under the module. agnd (a 2, b 2, c 2) zero dc voltage reference for the analog control circuitry. a small analog ground plane is recommended. vadj, ss, and vsense pins should be referenced to analog ground. these pins should be connected directly to the pcb analog ground plane. a single point connection between agnd and pgnd in motherboard is recommended . en (g 1) enable pin . wh en above enable on voltage (v en _on ), the power module will be turned on when the power input voltage (pvin) is above start up voltage (v start ). when en pin is below enable off voltage (v en_o ff ), the power module will be off. vadj (f 1) output voltage prog ramming pin . connect a resistor between this pin and pgnd top set the output voltage . vsense (e1 ) remote sensing pin. connect this pin to vout close to the load for improved voltage regulation. note : this pin is not connected to vout inside the module, a nd must be connected externally. nc (d1) there is no connection to this pin. leave open or connect to pgnd pwrgd (c 1) power good pin , an open drain output. a resistor connected between pwrgd and any voltage up to v in can be used. pwrgd is high if the out put voltage is higher than 9 0 % of the nominal value. it will be pulled down if the output voltage is less than 80% or higher than 120% of the nominal value.
spm1006 version 1.5 mar ch 16, 2016 page 6 of 22 lga package 73 pins , (top view) p h a s e a b c d e f g 1 2 3 4 5 6 7 8 9 1 0 1 1 p v i n a g n d e n v a d j v s e n s e s s p w r g d v a u x p g n d v o u t p g n d p g n d p v i n
spm1006 version 1.5 mar ch 16, 2016 page 7 of 22 typical efficiency and power loss data (note 1) a. efficiency and power loss at 12v input fig. 1 efficiency vs output current (v in =12v) fig. 2 power dissipation vs output current ( v in =12v ) b. efficiency and power loss at min, nominal and max input v out = 5v, t a = 25c fig. 3 efficiency vs output current (v out =5v) fig. 4 power dissipati on vs output current (v out =5v)
spm1006 version 1.5 mar ch 16, 2016 page 8 of 22 v out = 3.3 v, t a = 25c fig. 5 efficiency vs output current (v out =3.3v) fig. 6 power dissipation vs output current (v out =3.3 v) v out = 1.8 v, t a = 25c fig. 7 efficiency vs output current (v out =1.8 v) fig. 8 power dissipation vs output current (v out =1.8v)
spm1006 version 1.5 mar ch 16, 2016 page 9 of 22 v out = 1.0 v, t a = 25c fig. 9 efficiency vs output current (v out =1.0 v) fig. 10 power dissipation vs output current (v out =1.0v) v out = 0.6v, t a = 25c fig. 11 efficiency vs output current (v out =0.6v) fig. 12 power dissipation vs output current (v out =0.6v) not e 1: the above curves (figure 1 to figure 12) are derived from measured data taken on samples of the spm1006 tested at room temperature (25c), and are considered to be typical for the product.
spm1006 version 1.5 mar ch 16, 2016 page 10 of 22 application information output voltage programming the out put voltage is programmed using a resistor r prog from vadj to pgnd , as shown in fig. 13 . by default, the output voltage is 0.6 v without a resistor connected. note that the input voltage must be at least 1.5v higher than the ou tput voltage fig. 13 output voltage programming circuit a single standard 1% resistor can be used to program for any of the common voltages shown in table 1. table 1 - output voltage programming resistor 0.8 v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v 33.2 k 1 6. 5k 11 k 7.32 k 5.4 9k 3.48 k 2.43 k 1.5 k the programming resistor can be calculated for any output voltage using equation (1). (1) note that the vadj pin is noise sensitive and the connections to this pin should be kept as short as possible . to further adjust the output voltage, another resistor r trim may be connected between vsense and vadj, as shown fig. 14 . the resulting output voltage is a function of equation (2). (2) 1 6 . 0 / 11 ? ? ? v v k r out prog ) ) 11 11 * ( 1 ( * 6 . 0 prog trim trim out r k r k r v v ? ? ? ? ? v a d j v s e n s e r 1 r p r o g v o u t c o u t 0 . 6 v s p m 1 0 0 6 v o u t a g n d p g n d
spm1006 version 1.5 mar ch 16, 2016 page 11 of 22 fig. 14 output voltage trim circuit enable (en) control the en pin provides an electrical on/off control of the power module. once the voltage at the en pin exceeds the threshold voltage ( 0.8 v ) or is left open , the power module starts operation when the input voltage is higher than the input start up voltage (v start ) . when the voltage at en pin is pulled below the threshold voltage, the switching converter stops switching and the power module enters low quiescent current state. if an application requires con trolling the en pin, an open drain or open collector output logic can be used to interface with the pin, as shown in fig. 15 , where h igh on/off signal (l ow en) d isables the p ower m odule . fig. 15 typical on/off control when en pin i s open (or connected to a logic high voltage) , spm1006 produces a regulated output voltage following the application of a valid input voltage. fig. 16 shows the s tart up waveform for spm1006 without en control . the top trace is input voltage, the middle trace is power good signal (pwrgd), and the bottom trace is the output voltage. v a d j v s e n s e r 1 r p r o g v o u t c o u t 0 . 6 v s p m 1 0 0 6 v o u t a g n d p g n d r t r i m o n / o f f s i g n a l q 1 e n p g n d s p m 1 0 0 6
spm1006 version 1.5 mar ch 16, 2016 page 12 of 22 fig. 16 start - up waveforms for spm100 6 (set to 1.8v output) without en control fig. 17 and fig. 18 show the typical output voltage waveforms when spm1006 is turned on and turned off by the en pin. in these figures, the top trace is enable signal (en) , the middle trace is power good signal (pwrgd) , and the bottom trace is the output voltage. fig. 17 enable t urn - on for spm1006 (set to 1.8 v, with i out = 6a) fig. 18 enable turn - o ff for spm1006 (set to 1.8 v, with i out = 6a) the startup and shutdown waveforms are similar for other output voltages. pre - bias startup some applications require startup when there is a re sidual pre - bias voltage on the output. the spm1006 can start in this condition and as long as the pre - bias voltage is lower than the final output the start - up waveform will be normal. fig. 19 il l ustrates start up with pre - bias of approximately 50% of the nominal output voltage . fig. 20 shows the start - up when the pre - bias is about 80% of the nominal output.
spm1006 version 1.5 mar ch 16, 2016 page 13 of 22 fig. 19 start - up with pre - bias 2.62v (v out =5v) fig. 20 start - up with p re - bias 4.21 v (v out =5v) start up voltage by default, the spm1006 will turn on when the input voltage reaches the start up voltage (v start ). the spm1006 will turn off when the input voltage reduces to below the under volta ge lock - out (uvlo) level. start up voltage can not be reduced below t he values provided in the table of el ectrical characteristics. start up voltage can be increased by an external resistor (r en ) connected between en pin and pgnd pin. t he resistor value r en (in k?) can be calculated using equation ( 3 ) below based on the required start up voltage, v start . note: v start must be higher than 3.9v . ( 3 ) for example, to set the start - up voltage to 9.0v the value of r en will be 9.76 k . the shutdown voltage is given by equation (4) below: (4) for example, if r en = 9.76 k the shutdown voltage will be 4.5v. power good (pwrgd) the pwrgd pin is an open drain output . c onnect a pull up resistor (10k to 100k) between pwrg d pin and vaux pin, or to a suitable external voltage . [note: maximum voltage on this pin is v in , but any lower voltage logic level can be used.] pwrgd signal becomes high when the output voltage reaches 90 % of normal output voltage. the pwrgd signal becom es low when the output voltage is lower than 80% or higher than 120% of the normal output voltage. soft start operation soft - start operation is internal to the spm100 6. it has a n internally programmed fixed start - up time of 6 00us nominal for any output vo ltage setting and load current . ch1 blue = v in ch3 violet = pwrgd ch4 green = v out ch1 blue = v in ch3 violet = pwrgd ch4 green = v out ) 4 5 ( 400 ? ? start en v r en en shutdown r r v ) 100 ( * 4 . 0 ? ?
spm1006 version 1.5 mar ch 16, 2016 page 14 of 22 input and output capacitance recommended minimum capacitance is 47f ceramic (input) and 150f ceramic (output). additional capacitors can be connected in parallel if required , to reduce output ripple and improve transient r esponse. application schematics fig. 21 s hows a typical application schematic for 12 v input and 3.3 v output . startup voltage is set to 9v using the resistor r en , with value 9.76 k. if required, a mosfet can also be connected t o the en pin, as shown in fig. 15 to provide on - off control. fig. 21 typical s chematic for v in = 12 v, v out = 3.3 v with start - up voltage set to 9v sequencing operation the term sequencing is used when two or more separate modules a re configured to start one after the other, in sequence. sequencing operation between two or more spm100 6 power modules can be implemented with pwrgd pin and en pin. fig. 22 shows an example configuration when one spm100 6 (set to 5 v) starts first and a second spm1006 (set to 3.3 v) starts after the output voltage of the first spm1006 has reached 5 v . in this case, the power good signal (pwrgd) of the first module turns on the second module through the en pin . fig. 23 shows the output voltage waveforms of two spm100 6 modules used in sequential start - up mode. it shows that pwr gd signal becomes high when the first spm100 6 enters into regulation , and then the second spm100 6 starts up. note : the spm1006 can start in sequence with another spm1006 or with any other pol having a compatible power good output. all sumida power modules are fully compatible and can operate in sequence. v o u t 3 . 3 v p v i n 4 v t o 2 8 v c i n 1 2 4 7 f c i n 2 6 8 f c o u t 1 4 4 7 f e n v a u x s e n s e p g n d p w r g d v a d j v o u t p v i n a g n d s p m 1 0 0 6 p h a s e r p r o g 2 . 2 1 k ? r e n 9 . 7 6 k ?
spm1006 version 1.5 mar ch 16, 2016 page 15 of 22 fig. 22 sequen tial startup, v out1 = 5 v, v out2 = 3.3 v fig. 23 typical s equential startup waveforms ch1 blue = 3.3v output ch2 cyan = 5v output ch3 magenta = pg #1/en #2 p w g r d v o u t e n v o u t 1 5 v p w g r d v o u t e n v o u t 2 3 . 3 v s p m 1 0 0 6 # 2 s p m 1 0 0 6 # 1 v a d j r p r o g 1 . 3 7 k ? v a d j r p r o g 2 . 2 1 k ?
spm1006 version 1.5 mar ch 16, 2016 page 16 of 22 transient response spm100 6 uses instant pwm control and achieves excellent transient performance . the following table summarizes the measured data when the loa d current undergoes a step change between 2a and 5a for output voltage setting of 5v and input voltage of 12v . the slew rate for the load current change is 1a/s . v out setting transient voltage (3a step) recovery time 5v 40 mv 150s 50s transient response ( v in = 12v, v out = 5v) fig. 25 transient response ( v in = 12v, v out = 0.6v) th e above figure s show the typical output voltage waveform when th e load current undergoes a step change between 2 a and 5a (3a step) , showing that the spm100 6 can achieve excellent dynamic performance. over current protection for protection against over - current faults, spm100 6 will shut down when the load current is hig her than the over - current protection (ocp) level. during an over - current condition, spm100 6 will operate in hiccup mode and will try to re - start automatically. the hiccup operation will continue until the over - current condition is removed or input power is removed. fig. 26 shows the output voltage and outpu t current waveforms during over - current prot ection operation for spm1006 set to 1.8 v output . performance at other output voltage settings is similar. when the over - current condition is removed, the output voltage recovers automatically to the nominal voltage, as shown in fig. 27 .
spm1006 version 1.5 mar ch 16, 2016 page 17 of 22 fig. 26 overcurrent protection (hiccup mode) fig. 27 recovery from overcurrent input protection in most applications the input power source provides current limiting (typically fold - back or hiccup mode) and as long as the average fault current is limited to approximately 10a or less, no further protection is required. if the spm1006 is powered from a battery or other high current source , it is recommended to include an external fuse (maximum 10a) in the input to the module. the spm1006 includes full protection against output overcurrent or short - circuit , and the fuse will not operate under any output overload condition . for more i nformation refer to pm_an - 2 input protection. thermal considerations the maximum continuous current rating depends on the ambient temperature , input voltage and output voltage as shown in fig. 28 , fig. 29 and fig. 30 . output current can exceed th ese value s for short periods, as long as the average does not exceed the de rating curve. the peak current duration is limited by the thermal time constant , typically in the orde r of 60 seconds in most applications . the maximum rating is also influenced by the pcb layout; thermal performance can be improved by using more copper on the motherboard . th e de rating shown in these curves is measured using the sumida evaluation module ( evm ) layout . derating also depends on airflow; these curves are based on data measured under natural convection (no forced air). fig. 28 output current derating ( 6 .5 v input ) fig. 29 output current derating (12v input)
spm1006 version 1.5 mar ch 16, 2016 page 18 of 22 fig. 30 output current derating (24v input) for more information refer to application note pm_an - 3 spm1006 current ratings. the absolute maximum operating junction temperature is 1 50 c and it is recommended to keep the operating temperatu re well below this value under worst - case conditions. maximum recomm ended case temperature is 115 c, which corresponds to a junction temperature of approximately 125 c. the thermal resistance from case to ambient ( c a ) depends on the pcb layout as well as the amount of cooling airflow. when mounted on the evm, c a is appr oximately 15 c/watt in still air. please refer to the evm user guide for evm pcb layout information. the spm1006 implements an internal thermal shutdown to protect itself against over - temperature conditions. when the junction temperature of the power mosfe t is above 1 5 0c, the power module stops operating to protect itself from thermal damage. when the mosfet temperature reduces to approximately 13 5c (with hysteresis of 15c), spm1006 will restart automatically. layout considerations to achieve optimal electrical and thermal performance, an optimized pcb layout is required. some considerations for an optimized layout are: ? use large copper areas for power planes ( p vin, vout, and pgnd) to minimize con duction loss and thermal stress; ? place ceramic input and output capacitors close to the module pins t o minimize high frequency noise; ? locate additional output capacitors between the main ceramic capacitor and the load; ? connect agnd plane and pgnd plane at single point; ? place resistors and capacitors c onnected to sense and vadj pins as close as possible to their respective pins; ? do not connect phase pin to other components ; ? use multiple vias to connect the power planes to internal layers. refer to spm100 6 evaluation module (evm) user manual for suggeste d pcb layout .
spm1006 version 1.5 mar ch 16, 2016 page 19 of 22 mechanical data package dimensions and pcb pads all dimensions in millimeters
spm1006 version 1.5 mar ch 16, 2016 page 20 of 22 tape and reel packaging information fig. 31 tape dimensions and loading information fig. 32 reel d imensions spm1006
spm1006 version 1.5 mar ch 16, 2016 page 21 of 22 fig. 33 peel speed and strength o f cove r tape note : 1. the peel speed shall be approximately 300mm/min. 2. the peel force of the top cover tape shall be between 0.1n and 1.3 n. storage and handling moisture barrier bag the modules are packed in a reel, and then an aluminum foil moisture barrie r bag is used to pack the reel in order to prevent moisture absorption. silica gel is put into the aluminum moisture barrier bag as absorbent material. storage spm100 6 is classified msl level 3 according to jedec j - std - 033 and j - std - 020 standards, with a floor life of 168 hours after the outer bag is opened. any u nused spm100 6 modules should be resealed in the original moisture barrier bag as soon as possible. if the modules floor life exceeds 168 hours, the modules should be dehumidified before use by b aking in an oven at 125c/1% rh (e.g. hot nitrogen gas atmosphere) for 48 hours. handling precautions 1. handle carefully to avoid unnecessary mechanical stress. excessive external stress may cause damage. 2. normal esd handling procedures are recomme nded to be used whenever handling the module. 3. if cleaning the module is necessary, use isopropyl alcohol solution at normal room temperature. avoid the use of other solvents. 0.1 0 - 1.3 n
spm1006 version 1.5 mar ch 16, 2016 page 22 of 22 reflow soldering fig. 34 recommended reflow solder profile (lead - free) orderi ng information output voltage module part number pad finish package type temperature range adjustable spm1006 - z c au (rohs) lga - 40?c to 85?c 0.6v spm1006 - 0v6c 0.8v spm1006 - 0v8c 1.0v spm1006 - 1v0c 1.2v spm1006 - 1v2c 1.5v spm1006 - 1v5c 1.8v spm1006 - 1v8c 2.5v spm1006 - 2v5c 3.3v spm1006 - 3v3c 5.0v spm1006 - 5v0c

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